Tenstorrent jobs: what your CV needs to get read
Quick answer: Tenstorrent announced a $1.5 billion Series E at a $6.2 billion valuation on 19 October 2026 and is hiring across RISC-V CPU, AI hardware, compiler and kernel teams. A CV that gets read names the stack explicitly — C++, SystemVerilog, MLIR, RISC-V — proves performance wins with numbers, points to verifiable open-source commits, and stays in a single-column format its applicant tracking system can parse.
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What just happened at Tenstorrent, and why does it change your CV?
Tenstorrent closed a $1.5 billion Series E on 19 October 2026 at a $6.2 billion post-money valuation, and the company has been explicit that the money funds volume manufacturing and global commercial expansion rather than an exit. That roughly doubles the $2.6 billion it was worth after its December 2024 round, when it raised more than $693 million. Takeover conversations with Intel and Qualcomm were reported earlier in the year; the company chose to raise and stay independent instead. CEO Jim Keller has pointed to a May demonstration of its Galaxy servers running high-performance DeepSeek models as the moment the commercial case clicked. Trace Capital and Innovation X led, with Fidelity, T. Rowe Price, ARK Invest, Sandisk and Morgan Stanley among the names joining.
Staying independent means staying on the hook for headcount. Tenstorrent's job board has been carrying roughly a hundred-plus open engineering roles, grouped into teams you can read straight off the page: AI Hardware and Tensix, AI Software, Architecture, Design Verification, Advanced Physical Design. Offices span Toronto, Austin, Santa Clara, Fort Collins, Boston, Belgrade and Bengaluru, plus Tokyo, Seoul, Taiwan and a scattering of remote-friendly postings. Published engineering compensation runs from about $100,000 to $500,000 including base and variable targets — a band wide enough that the level you're hired at depends heavily on how convincingly your CV argues for seniority.
Here's the bridge to your document. A funded, independent Nvidia challenger with triple-digit openings is the most attractive silicon employer most hardware engineers will see this year, which means the applicant pile has just grown faster than the team. Postings repeatedly say they welcome contributors of all seniorities and assess level during interviews, so the CV's job isn't to claim a title — it's to make the technical depth legible in about eight seconds of scanning. That favours specifics over adjectives: the node you taped out on, the kernel you sped up, the dialect you wrote passes for.
Which keywords do Tenstorrent job postings actually use?
The vocabulary that matters sits in two columns: the open-source software stack and the silicon disciplines. On the software side, postings name TT-Forge, the MLIR-based compiler that takes models from PyTorch, JAX, ONNX and TensorFlow and lowers them through TT-MLIR to TT-NN and TT-Metalium kernels, with TT-LLK underneath. Compiler roles ask for C++ and Python fluency, MLIR experience or strong interest, and comfort building custom dialects and transformation passes — the stack's own dialects are TTIR, TTNN and TTKernel. Kernel roles ask for matmul and attention primitives, data movement, host-side orchestration, micro-benchmarks and regression tooling. Write those words, not "AI/ML" and "deep learning".
On the hardware side the asks are conventional silicon engineering, stated precisely. CPU roles want RISC-V microarchitecture: pipelines, out-of-order execution, register renaming, branch prediction, cache hierarchies, and the vector and matrix ISA extensions that make an AI core interesting. Design verification roles want SystemVerilog and SystemVerilog Assertions, test plans, functional coverage points and convergence toward tape-out, with formal verification appearing as its own discipline. Physical verification postings get granular: DRC, LVS, ERC, PERC, antenna and DFM checks with Calibre, ICV, Pegasus or Innovus, plus ESD planning, padring integration, bump and RDL work, IR-drop and electromigration analysis on 7nm, 5nm and 3nm FinFET nodes, scripted in Python and TCL.
One contrarian note, and I'll defend it: naming the hardware generations buys you more credibility than naming the frameworks. Anyone can write PyTorch. Writing that you benchmarked on a Wormhole n150 or n300 card, or a Blackhole p150, or that you ran TT-Metalium workloads under ttsim because you didn't have silicon on your desk, tells a hiring manager you've touched the actual platform. The same applies to the architectural detail that trips newcomers up — each Tensix core has 1.5 MB of local SRAM used as a software-managed scratchpad rather than a hardware cache, so placement, tiling and staging are yours to manage. Say you've done that.
| Layer or domain | What it actually is | How to write it on your CV |
|---|---|---|
| TT-Forge / TT-MLIR | Open-source MLIR compiler stack lowering PyTorch, JAX and ONNX models onto the hardware | Name MLIR, custom dialects and transformation passes, and which framework you brought models in from |
| TT-NN / TT-Metalium | Operator library plus the low-level C++ SDK for writing kernels on Tensix cores | List kernel work by name: matmul, attention primitives, data movement, circular buffers |
| TT-LLK and ISA level | Low-level kernels, vector and matrix operations, custom ISA extensions | Cite intrinsics or assembly work and any custom extension you used or helped define |
| RISC-V CPU | Custom high-performance cores and IP licensed to other chip designers | Microarchitecture depth: pipelines, out-of-order, renaming, branch prediction, caches |
| Design verification | Test plans, testbenches and coverage convergence toward tape-out | SystemVerilog, SVA, formal; coverage closure numbers and bugs caught pre-silicon |
| Advanced physical design | Full-chip PD, timing and physical verification on FinFET nodes | DRC, LVS, ERC, antenna, DFM, STA, IR drop, EM, plus node and Python/TCL scripting |
How do you frame Nvidia and CUDA experience without sounding locked in?
Lead with the problem you solved, not the API you solved it in. Tenstorrent's whole pitch is an open alternative to a CUDA-anchored ecosystem, so a CV that reads as a list of vendor-specific tooling invites the obvious doubt: can this person think below the abstraction? The fix is one layer of translation per bullet. "Wrote fused attention kernels in CUDA" becomes "Wrote fused attention kernels: tiled the problem to fit on-chip memory, double-buffered loads to hide latency, lifted throughput 2.4× over the library baseline." Same work, now portable. The hiring manager reads tiling, data movement and latency hiding — exactly the reasoning a software-managed scratchpad architecture demands.
Then name the architectural translation out loud, because nobody will do it for you. A GPU programmer's instincts about warps, occupancy and coalesced access map onto a different machine here: three user kernels program a single Tensix core — one for each data-movement RISC-V core and one for compute — and circular buffers carry data between them. If you've written code that explicitly stages data rather than leaning on a cache to guess, say so. One honest sentence in your summary does real work: "Six years of GPU kernel optimisation; moving to explicit dataflow architectures because that's where the performance ceiling actually is."
Build a small piece of verifiable proof before you apply. You don't need hardware: the full-system simulator runs TT-Metalium workloads on an ordinary Linux x86-64 machine, and both the kernel SDK and the compiler stack are open source under Apache 2.0. Port one operator, benchmark it, write up what you learned about the memory model, and put the repository link in your CV header. That single line beats a paragraph of self-assessment, and it answers the "locked in" question permanently. When your CV is drafted, a free AI CV analysis will tell you whether that reframing actually reads as impact or still reads as a tool list.
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Which projects should you lead with for the hardware or software track?
Lead with the artefact closest to silicon shipping. For hardware applicants, that's a block you owned through tape-out, named by function and node — "L2 cache controller, 5nm, 1.2 GHz, led coverage closure to sign-off" — followed by your silicon bring-up and debug work, which is the rarest skill on any CV in this market. For software applicants, it's a kernel or compiler pass you landed with a before-and-after number attached: throughput, latency, tokens per second, or percentage of theoretical peak reached. Everything else on the page is context for that one project, and if the top third of page one doesn't contain it, you've buried your own case.
Resist the urge to flatten your history into one generic document. Design verification, physical design and CPU architecture are assessed by different panels asking different questions, and a posting at 7–14 years of physical verification experience is not reading the same CV as a Boston DV role pitched at 3–5 years. Keep one base CV and three tailored variants, each reordering the projects and the skills block to mirror the job ad. If you'd rather not maintain that by hand, an AI CV builder that keeps the formatting ATS-safe will spin role-specific versions off your existing file without you rebuilding the layout each time.
Quantify in the units your reader uses. Verification engineers trade in coverage percentages, bug counts and escapes; physical design engineers in timing margin recovered, IR-drop violations cleared and area saved; compiler engineers in compile time and graph-level speedups; kernel engineers in achieved bandwidth against roofline. Vague impact claims are where strong candidates lose to mediocre ones who happened to write numbers down. If you're structuring this from scratch, the same logic behind a section-by-section build for ASIC and RTL engineers applies here — prove judgment and measurable outcomes, not years served.
| Evidence type | Hardware track (RISC-V, DV, physical design) | Software track (compiler, kernel, runtime) |
|---|---|---|
| Lead project | A block you owned to tape-out, with function and node | A kernel or compiler pass you landed, with before/after throughput |
| Headline number | Coverage closure, bugs caught pre-silicon, timing or power margin recovered | Latency or throughput gain, percentage of roofline achieved |
| Tooling line | SystemVerilog, SVA, Calibre, ICV, Pegasus, Innovus, STA, Python, TCL | C++, Python, MLIR/LLVM, PyTorch, JAX, profilers, micro-benchmark harnesses |
| Verifiable proof | Tape-out count plus hands-on bring-up and silicon debug | Public commits to the open-source stack or a benchmarked simulator project |
What gets a Tenstorrent application screened out before a human reads it?
Formatting and eligibility, far more often than talent. Applications go through Greenhouse, which parses your file into structured fields before anyone opens it, and parsers reliably mangle two-column layouts, text boxes, icons, header-and-footer contact details and skills rendered as rating bars. A dense single-column PDF with plain section headings, real dates and your stack written as text survives extraction intact. Separately, US postings state that offers are contingent on eligibility to access export-controlled technology, with restrictions tied to certain country groups — so if you hold a status that clears this, put it plainly in one line near your contact block rather than leaving a recruiter to guess.
Make the match obvious in the first six lines. Tenstorrent's teams are named on the board — AI Hardware, AI Software, Architecture, Design Verification, Advanced Physical Design — and the locations are specific. A professional summary that says "RISC-V CPU verification engineer, 6 years, SystemVerilog and formal, two tape-outs, Austin-based and on-site capable" answers every screening question in one sentence. Generic openers about being a passionate innovator in cutting-edge technology answer none of them. Add your GitHub handle if you've contributed to the open-source stack; commits in the compiler or kernel repositories are the cleanest signal a candidate can send, and they're trivially checkable.
Before you submit, run the file through the same kind of automated read the employer will. A Greenhouse-specific resume check will show you whether your dates, job titles and skills section come out the other side as readable fields or as scrambled text, and whether your ATS compatibility score is actually holding up. Paste the job description in too, and you'll get a list of the skills the posting asks for that your CV never mentions — which, for roles this keyword-dense, is usually the difference between a screen and silence. Fix the gaps, re-export, then apply.
Frequently asked questions
What are Tenstorrent's careers requirements for engineers?
Most postings ask for C++ fluency plus genuine depth in one discipline: RISC-V microarchitecture, SystemVerilog and coverage-driven verification, MLIR-based compiler work, kernel optimisation, or physical design on FinFET nodes. Experience bands vary widely — a Boston DV role sat at 3–5 years while full-chip physical verification asked for 7–14. Postings say contributors of all seniorities are welcome and level is set in interviews, and US offers require eligibility for export-controlled technology.
How do I get a job at Tenstorrent without AI-accelerator experience?
Build the evidence yourself. The kernel SDK and compiler stack are open source, and the full-system simulator runs real workloads on any Linux x86-64 machine, so you can port an operator, benchmark it and publish the result without owning hardware. Pair that with transferable depth — GPU kernel tuning, HPC performance work, CPU verification — reframed around tiling, explicit data movement and latency hiding rather than vendor-specific APIs.
Which RISC-V resume keywords should an AI chip engineer include?
Use the terms the postings use: RISC-V, custom cores, vector and matrix ISA extensions, out-of-order execution, register renaming, branch prediction, cache hierarchy, RTL, Verilog and SystemVerilog, SVA, formal verification, power management, and system software such as drivers, firmware and runtime. For the software side add MLIR, LLVM, custom dialects, transformation passes, C++, Python, PyTorch and JAX. Only list what you can discuss for ten minutes under questioning.
Does Tenstorrent's $1.5B raise mean it's hiring more aggressively?
The company said the Series E funds volume manufacturing and global commercial expansion, and it chose to raise rather than sell after reported takeover talks with Intel and Qualcomm. Its job board has carried roughly a hundred-plus openings across Toronto, Austin, Santa Clara, Belgrade, Bengaluru and Asia-Pacific offices. Published engineering compensation runs about $100,000 to $500,000 including variable pay, which means the level your CV argues for matters financially.
Is your CV good enough?
Upload your CV and get an instant AI score out of 100, an ATS-compatibility rating and a breakdown across five categories — free.